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VHDL多功能时钟设计
- VHDL多功能时钟设计~~24小时制~带闹钟,VHDL design of multi-functional clock ~ ~ ~ 24 hours with alarm system
VHDL-ROM4.基于ROM的正弦波发生器的设计
- 基于ROM的正弦波发生器的设计:1.正弦发生器由波形数据存储模块(ROM),波形发生器控制模块及锁存模块组成 2.波形数据存储模块(ROM)定制数据宽度为8,地址宽度为6,可存储 64点正弦波形数据,用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 ,ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), wav
DS1307_LCD.通过IIC总线读写实时时钟DS1307
- 通过IIC总线读写实时时钟DS1307,并把时、分、秒显示在12864液晶屏上,用的CycloneII EP2C8,Quartus环境,Through the IIC bus read and write real-time clock, DS1307, and the hours, minutes and seconds displayed on the LCD screen on the 12864, used CycloneII EP2C8, Quartus environment
VHDL
- 1、 设计一个简易电子琴。要求能演奏的音域为中音的 1 到高音的 1。 2、 用GW48-PK2中的8个按键作为琴键。 3、 GW48-PK2中有扬声器。 4、 可以使用GW48-PK2上的12MHz作为输入时钟信号。 -1, the design of a simple flower. Requirements can play for the tenor of the range of 1 to treble the 1.2, and GW48-PK2 in eight ke
CLOCK
- 文通过ALTERA公司的quartus II软件,用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为:计时功能,24小时制计时显示;通过七段数码管动态显示时间;校时设置功能,可分别设置时、分、秒;跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital
50M
- verilog 语言写的分频模块,实现用50Mhz的时钟频率分出1hz的频率,也就是一秒的频率-verilog language sub-frequency module, using the 50Mhz clock frequency 1hz separation, that is, the frequency of second
vhdl
- 基于vhdl的数字时钟;24制,带有定时,闹钟等功能。-VHDL-based digital clock 24 system, with time, alarm clock functions.
clock
- EDA 数字钟实现文件 能够实现计时,闹钟,校时功能 -EDA digital clock time to achieve the realization of paper, alarm clock, school functions
clock
- 用verilog语言实现数字时钟,有注释,规范-Digital clock using verilog language, there are notes, specifications
clock
- 描述了24小时计时的数字钟,同时具有分秒计时的功能-Described a 24-hour digital time clock, at the same time every minute timer function
clock
- 基于VHDL的电子时钟设计-VHDL-based design of an electronic clock
clock
- 可以实现时间调节,十二,二十四小时转换,定时,闹钟的时钟-Can be time-conditioning, 12, 24 hours conversion, time, alarm clock
alarm-clock
- 基于vhdl的数字闹钟的设计。可实现计时、闹钟、调节时间功能。可以在FPGA上实现。-VHDL-based digital alarm clock design. Can achieve a time, alarm clock, adjust time function. FPGA implementation can be on.
clock
- 数字钟是采用数字电路实现“时”、“分”、“秒”数字显示的计时装置。由于数字集成电路的发展和石英晶体震荡器的使用,使得数字钟的精度、稳定度远远超过了机械钟表,已成为人们日常生活中必不可少的必需品。-Digital Clock is a digital circuit implementation, " when" , " sub" , " second" The figures show that the timing device. Digita
clock
- 这是一个电子时钟的VHDL语言程序,非常好,注释也比较清晰,它包括电子时钟的所有功能。-This is an electronic clock VHDL language program, very good, the Notes are also clear, which includes all the features of the electronic clock.
clock
- VHDL数字闹钟实现,运用八位LED显示-VHDL realization of the digital alarm clock, the use of eight LED display
clock
- 电子时钟,能够进行计时,可设定闹钟,可以当做跑表,并且可以更改时间-electric clock
FPGA-clock
- 基于VHDL的时钟设计(de2开发平台),内含源代码,各模块的时序仿真图,结构原理图,以及完成报告。供大家参考学习。-VHDL-based clock design (de2 development platform), contains the source code, simulation charts of each module, structure diagram, and the mission report. For reference study.
digital-clock-design
- VHDL语言编写的数字时钟设计程序,含源代码和波形仿真,还有顶层电路设计。-The VHDL language of the digital clock design procedures, including source code and the waveform simulation, but also the circuit design.
clock
- there's a clock divider for DE2 altra board clock (50MHz)